FPGA / Embedded Systems Developer

Deterministic systems, made observable.

I develop FPGA, embedded, and scientific-computing systems where correctness depends on explicit timing, bounded arithmetic, coherent sensor publication, and evidence that can be inspected at the bench.

Current work spans Verilog RTL for avionics and sonar-vision instrumentation, fixed-point estimation and safety-gated control, telemetry contracts, MATLAB validation environments, and C/C++ simulation tools.

Review selected work Read engineering case studies

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3FPGA platforms

RTLDeterministic, reviewable design

CDCExplicit domain boundaries

HILInstrumentation-first verification

Selected work

Systems under active development

Project status is stated conservatively: repository integration, focused verification, tool-flow validation, and hardware evidence are not treated as interchangeable claims.

01 Active development

Basys 3 · Verilog · VGA · I²C/SPI/UART

CaelumFusion Flight Control System

A Basys 3 avionics instrumentation stack built around deterministic sensor snapshots, explicit provenance and freshness, CDC-safe publication, VGA diagnostic surfaces, and host-visible evidence.

Board-facing integration through caelumfusion_top_vga.
Raw and derived telemetry banks carry validity, status, sequence, age, and source information.
Includes fixed-point estimator and apogee-authority policy RTL, focused benches, black-box frame packing, and scripted Vivado flows.

Present evidence boundary Integrated source, project metadata, targeted testbenches, and release checklists are present. Fresh matching-version synthesis, implementation, timing closure, and complete hardware signoff remain explicit gates.

Open repository Read case study

02 Canonical analysis package

MATLAB · Telemetry · Estimator replay

Offline Flight Analysis Dashboard

The offline counterpart to the flight-control stack: import, schema normalization, estimator replay, engineering dashboards, and firmware-to-analysis contract validation for captured SD and serial telemetry.

Vertical-state replay with innovation, covariance, bias, beta, and gating diagnostics.
Integrated review surfaces for sensor health, uncertainty, GPS, trajectory, wind, mission phase, policy, and provenance.
A release entry point runs firmware alignment, replay, mission-profile, and live-import validation gates.

Open repository Read case study

03 Phase 4 integration

Nexys Video · HDMI · Camera · Sonar

AquaFusion Sonar Vision System

A multi-clock sonar and camera fusion HUD for the Nexys Video, combining Pcam 5C control, sonar publication, occupancy-map painting, frame-committed telemetry, HDMI composition, OLED output, and dedicated debug surfaces.

Region-qualified HDMI composition replaces unsafe black-pixel transparency.
SYS-to-VID snapshot CDC and frame-boundary commits keep telemetry coherent on screen.
Isolated camera, sonar-map, UART, radar, painter, and status views support staged bring-up.

Known limits The camera viewport is a raster clip rather than a scaler; Sonar 2 is tied off; bearing validity is not yet supplied by the live fusion path; CLS integration is currently commented out.

Open repository Read case study

FPGA Signal Control System hardware and visualization setup

04 Integrated system

Nexys A7-100T · ToF · PWM · VGA · UART

FPGA Signal Control System

A single-clock, hardware-only spatial mapping and temperature-control laboratory integrating ToF measurement, XADC temperature, PIR conditioning, fan-control logic, VGA visualization, and 2 Mbit/s telemetry.

Open repository Read case study

Simulation, visualization & tooling

Additional engineering work

View detailed notes

Library hardening

OpenFrameworks User Interface Library

A reusable C++ widget system for scientific visualization: buttons, toggles, validated text fields, sliders, tables, table managers, tooltips, and drag-selection tools with programmatic layout and callbacks.

Repository

Simulation logic complete

Generic Quadtree Barnes–Hut N-Body Simulator

A real-time 2D C++/openFrameworks simulator using adaptive pointer-based quadtrees and Barnes–Hut force approximation. Current work centers on UI and architecture refactoring for reuse and educational clarity.

Repository

Research prototype

Serial Hashed-Octree Barnes–Hut N-Body Simulator

A 3D exploration of Morton-ordered hashed octrees, adaptive spatial decomposition, memory locality, and force approximation as a foundation for future parallel construction and traversal.

Repository

Visualization

Fourier Geometric Visualization

An interactive openFrameworks visualization that decomposes a drawn path with the discrete Fourier transform and reconstructs it through rotating harmonic circles.

Repository

Data systems

Automated CSV Data Analysis

A modular C pipeline for heterogeneous dataset ingestion, schema and type inference, cleaning, column extraction, descriptive statistics, normality analysis, and generation of downstream MATLAB modeling artifacts.

Repository

MATLAB UI

Programmatic Scientific Calculator

A modular, source-controlled MATLAB calculator built entirely with native programmatic UI components, custom expression validation, editable input, and scrollable command history.

Repository

Capabilities

End-to-end engineering across the evidence chain

The common thread is not a single language or board. It is the design of systems whose assumptions, timing, state, and failure modes remain inspectable from sensor input through rendered output.

FPGA / RTL

Verilog, synchronous architecture, CDC, reset release, fixed-point arithmetic, I²C/SPI/UART, PWM, BRAM, VGA/HDMI pipelines, and Vivado integration.

Embedded systems

ARM Cortex-M, Teensy, HCS12, sensor and actuator interfaces, packet protocols, command gating, telemetry logging, and hardware-software partitioning.

Estimation & control

Kalman filtering, covariance and innovation diagnostics, sensor provenance, fixed-point modeling, safety-gated policy logic, and bounded command behavior.

Scientific computing

C/C++17, MATLAB, Barnes–Hut methods, quadtrees and hashed octrees, numerical simulation, data pipelines, visualization, and performance-oriented design.

Verification

Focused testbenches, golden-vector workflows, synthesis and timing gates, protocol decoding, structured acceptance criteria, and failure-oriented review.

Bench instrumentation

Analog Discovery and WaveForms captures, probe planning, trigger conditions, serial framing checks, clock and pulse-width measurements, and correlated host analysis.

Selected technical writing

Reports, studies, and design documentation

Long-form work supporting the implementations above, including architecture, derivation, design decisions, and experimental context.

FPGA / VisionAquaFusion Phase 4 Stage A Report · 01Open document FPGA / VisionAquaFusion Phase 4 Stage A Report · 02Open document FPGA / VisionAquaFusion Phase 4 Stage A Report · 03Open document AlgorithmsA Study of the Barnes–Hut Approximation AlgorithmOpen document FPGA / ControlFPGA Signal Control System ReportOpen document Data systemsAutomated CSV Data Analysis FrameworkOpen document VisualizationFourier Series Harmonic Circles / Epicycle VisualizationOpen document Analog designVoltage Regulator DesignOpen document SimulationReal-Time Quadtree Barnes–Hut N-Body SimulationOpen document Software educationECE 370 Quadratic Quiz Generator · 01Open document Software educationECE 370 Quadratic Quiz Generator · 02Open document

Independent research proposalDissecting the Mechanisms of Action in Alopecia AreataLink available upon request

About

Engineering from interfaces inward.

I am a Computer Engineering undergraduate at the University of Michigan–Dearborn, focused on embedded systems, FPGA design, numerical estimation, telemetry, and scientific visualization.

My projects typically begin at a real interface—a sensor bus, an asynchronous control, a telemetry packet, a pixel stream, or a scientific dataset—and proceed through explicit contracts until the resulting behavior can be measured. That approach has led me across RTL, firmware, MATLAB analysis, C/C++ simulation, and the instrumentation required to connect them.

I am interested in engineering and research environments where timing, observability, numerical behavior, and careful verification matter as much as feature completion.

Contact

Let’s discuss the system behind the demo.

Open to embedded, FPGA/RTL, verification, controls, scientific-computing, and technical visualization opportunities.

02richardsondavid@gmail.com Connect on LinkedIn