FPGA systems
Instrumentation-led RTL development
Each design separates data production, cross-domain publication, rendering or control policy, and evidence collection so failures remain localizable.
CaelumFusion is an FPGA-side avionics instrumentation environment rather than a claim of flight-ready autonomy. Its core concern is the trustworthy movement of evidence: from physical or synthetic producers, through typed snapshot contracts and domain crossings, into diagnostic visualization, logging, and policy observability.
System architecture
caelumfusion_top_vga owns the Basys 3 board interface and integration boundary.- I²C, SPI, GPIO, and UART producers publish payload, timestamp, sequence, validity, status, age, and source provenance.
- SYS-domain visualization state crosses into the pixel domain through coherent toggle/snapshot CDC before frame-stable VGA rendering.
- Extension evidence includes range, dual-magnetometer comparison, power, fault injection, guarded navigation/wind fields, and a versioned black-box stream.
Estimator and authority work
- A fixed-point altitude/vertical-speed Kalman core and focused testbench are present.
- Apogee-authority policy RTL is integrated into the visualization model as deterministic policy evidence.
- Phase and safety-gate observability are separated from the final command owner.
- The present policy remains an engineering model, not a calibrated aerodynamic controller.
Evidence currently present
- Hand-authored RTL, XDC, Vivado project metadata, focused testbenches, Tcl flows, host decoders, and release checklists.
- Targeted benches cover sensor-suite behavior, MAG1, PMON1, extension metadata, fault injection, render selection, science-page pixels, and UART bridge handling.
- Generated runs and bitstreams are intentionally excluded from source control.
Next verification gate
- Normalize the Vivado-version boundary around the project metadata.
- Run fresh-library simulations and archive commit-specific PASS evidence.
- Complete synthesis, implementation, DRC, CDC review, and timing closure in the selected tool version.
- Finish external-UART and board-level sensor/display capture evidence before flight-style signoff.
The dashboard closes the loop between embedded telemetry and engineering review. It imports SD or serial logs, normalizes changing firmware schemas, reconstructs estimator behavior, and exposes uncertainty, freshness, causality, provenance, policy, and mission context without collapsing them into a single polished trajectory.
Data contract
- Strict and recovery-oriented import paths for SD CSV and firmware
HDR/TLM serial captures.
- Schema checks retain field order and separate firmware control targets from the IREC mission target.
- Representative fixtures remain tracked; regenerated exports and local captures remain ignored.
Engineering analysis
- Vertical replay surfaces innovation, covariance, bias, beta, and gate decisions.
- Optional attitude, gravity-provenance, 3D/GPS EKF, wind, causality, and Monte Carlo views support deeper review.
- Integrated dashboards cover flight state, sensor health, trajectory, policy, phase, uncertainty, and summary evidence.
Release gate
validate_caelum_release runs firmware/dashboard alignment, vertical-replay, IREC mission-profile, and live-telemetry-import checks, reporting an overall pass and throwing on a required-gate failure.
AquaFusion combines camera, sonar, occupancy-map, telemetry, and debug surfaces across SYS, VID, and TMDS domains. The current Phase 4 work concentrates on reliable composition and observability: a visible panel should establish which portion of the path is alive even when upstream data is absent.
SYS producersCamera control, sonar UART/PWM, status
Snapshot CDCStable multi-bit publication into VID
Frame commitUser-visible state changes at boundaries
CompositionGeometry-qualified camera, map, radar, UART, debug
Recent integration progress
- Replaced black-pixel transparency with explicit region ownership.
- Added a bounded camera HUD viewport while retaining full-screen camera diagnostics.
- Added an isolated sonar-map debug view and visible fallback panel shell.
- Corrected dual-port map-memory read latency and low-occupancy color handling.
- Corrected post-reset publication of the auxiliary view selector.
Sonar and display path
- Sonar 1 can publish raw or filtered range evidence with watchdog, age, status, and rich telemetry.
- The occupancy painter writes a dual-clock map consumed by a VID-domain renderer and region-qualified compositor.
- Camera and sonar state are independently visible through diagnostic modes, lowering bring-up ambiguity.
- OLED telemetry remains a separate SYS-domain output rather than an HDMI dependency.
Implemented boundary
Repository source establishes the top-level integration, subsystem modules, view controls, CDC structure, map path, and staged bring-up sequence.
Known limits / next gate
Sonar 2 remains disabled; live bearing validity is not yet supplied; the HUD viewport does not scale; CLS is commented out. Elaboration, simulation, implementation/timing, and bench evidence must remain separately reported.
A hardware-only spatial mapping and temperature-control lab built as a single-clock design. Clock enables pace slow functions while sensing, control, graphics, and telemetry remain synchronous to the 100 MHz board clock.
Sensing
ISL29501 ToF over I²C, XADC temperature in Q1.15, PIR conditioning, and rotary surveyor input.
Control
Temperature, occupancy, and manual fan contributions feed an FSM and PWM drive with hysteresis and visible source flags.
Visualization
640×480 VGA range plotting and HUD output, a double-buffered RGB444 viewport, and CRC-framed UART telemetry at 2 Mbit/s for MATLAB decoding.